PCI2050BIPDV

Product Summary

The PCI2050BIPDV is a PCI-to-PCI bridge. It provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050BIPDV bridge allows bridged transactions to occur concurrently on both buses. The bridge PCI2050BIPDV supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

Parametrics

PCI2050BIPDV absolute maximum ratings: (1)Supply voltage range: VCC: -0.5 V to 3.6 V; P_VCCP: -0.5 V to 6 V; S_VCCP: -0.5 V to 6 V; (2)Input voltage range, VI: CMOS: -0.5 V to VCC + 0.5 V; (3)Input voltage range, VI: PCI: -0.5 V to 6 V; (4)Output voltage range, VO: CMOS: -0.5 V to VCC + 0.5 V; (5)Output voltage range, VO: PCI: -0.5 V to 6 V; (6)Input clamp current, IIK (VI < 0 or VI > VCC): ±20 mA; (7)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (8)Storage temperature range, Tstg: -65 to 150℃; (9)Virtual junction temperature, TJ: 150℃.

Features

PCI2050BIPDV features: (1)Two 32-bit, 66-MHz PCI buses; (2)3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments; (3)Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter; (4)Ten secondary PCI clock outputs; (5)Independent read and write buffers for each direction; (6)Burst data transfers with pipeline architecture to maximize data throughput in both directions; (7)Supports write combing for enhanced data throughput; (8)Up to three delayed transactions in both directions; (9)Supports the frame-to-frame delay of only four PCI clocks from one bus to another; (10)Bus locking propagation; (11)Predictable latency per PCI Local Bus Specification; (12)Architecture configurable for PCI Bus Power Management Interface Specification; (13)CompactPCI hot-swap functionality; (14)Secondary bus is driven low during reset; (15)VGA/palette memory and I/O decoding options; (16)Advanced submicron, low-power CMOS technology.

Diagrams